Scalable spatiotemporal interleaving network for high-density integrated photonic convolution

Efficient edge intelligence is fundamentally constrained by data movement overhead in conventional electronic hardware, motivating alternative computing paradigms with intrinsic parallelism. Although integrated photonic processors provide multiple parallel dimensions, established architectures remain limited by the quadratic scaling of both footprint and control complexity with rising computational throughput. Here, we propose an on-chip spatiotemporal photonic interleaving network (SPIN) that enables convolutional acceleration by recursively interleaving distributed delay lines into shared physical channels, thereby redistributing throughput scaling from spatial replication to wavelength multiplexing while reducing waveguide footprint to O(K log₂ K) and active control complexity to O(K). Experimental results demonstrate high-fidelity convolution with a correlation coefficient exceeding 0.98 on the Modified National Institute of Standards and Technology (MNIST) dataset, complemented by programmable multi-task operation and configurable kernel geometry. The SPIN architecture is capable of supporting a projected single-core throughput of 29.7 TOPS upon full exploitation of the available spectrum. These results validate a structurally scalable and energy-efficient photonic computing framework, advancing the viability of integrated optical accelerators for next-generation edge AI.