Abstract: This article studied the frame structure of Xilinx FPGA configuration RAM, giving the method of extracting the frame structure and providing the order of frames in the bit stream file. The structure of the intermediate file of SEM IP core is also analyzed to get the positions of essential bits. Performing 0/1 flipping on the essential bits is a way to simulate the single event upset which the circuit is sensitive to under the radiation environment. A PC-side interface is designed to implement a human-machine interaction. The fault injection system is implemented on the FPGA chip, and the read and write of configuration RAM data are realized through ICAP without the need of the processor. The operation of flipping and repairing test classifies essential bits into some categories. The classification results can be used to protect the key bits in subsequent fault repairing.