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Qi HX, Du ZC, Hu XY, Yang JY, Chu SS et al. High performance integrated photonic circuit based on inverse design method. Opto-Electron Adv 5, 210061 (2022). doi: 10.29026/oea.2022.210061
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High performance integrated photonic circuit based on inverse design method
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Abstract
The basic indexes of all-optical integrated photonic circuits include high-density integration, ultrafast response and ultra-low energy consumption. Traditional methods mainly adopt conventional micro/nano-structures. The overall size of the circuit is large, usually reaches hundreds of microns. Besides, it is difficult to balance the ultrafast response and ultra-low energy consumption problem, and the crosstalk between two traditional devices is difficult to overcome. Here, we propose and experimentally demonstrate an approach based on inverse design method to realize a high-density, ultrafast and ultra-low energy consumption integrated photonic circuit with two all-optical switches controlling the input states of an all-optical XOR logic gate. The feature size of the whole circuit is only 2.5 μm × 7 μm, and that of a single device is 2 μm × 2 μm. The distance between two adjacent devices is as small as 1.5 μm, within wavelength magnitude scale. Theoretical response time of the circuit is 150 fs, and the threshold energy is within 10 fJ/bit. We have also considered the crosstalk problem. The circuit also realizes a function of identifying two-digit logic signal results. Our work provides a new idea for the design of ultrafast, ultra-low energy consumption all-optical devices and the implementation of high-density photonic integrated circuits. -
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References
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Qi HX, Du ZC, Hu XY, Yang JY, Chu SS et al. High performance integrated photonic circuit based on inverse design method. Opto-Electron Adv 5, 210061 (2022). doi: 10.29026/oea.2022.210061
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Figure 1.
Design optimization process of the all-optical switch. (a) General configuration of the all-optical switch. (b) The initialization and discrete optimization permittivity distribution in the x-y two-dimensional cross-section, where bias=0 and bias=infinity.
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Figure 2.
Characterization of the all-optical switch. (a) The “ON” state of normalized intensity distribution in the x-y plane from theoretical calculation. (b) The “OFF” state of normalized intensity distribution in the x-y plane from theoretical calculation. (c) Scanning electron microscopy (SEM) image of the all-optical switch. The size of the optimized area was 2 μm×2 μm. (d) Simulation results of the transmission of all-optical switch. (e) Experiment results of the normalized transmission of all-optical switch. (f) The simulation and experiment results of the all-optical switch ON/OFF contrast.
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Figure 3.
Characterization of the all-optical switch. (a) The “OFF” state of normalized intensity distribution in the x-y plane from theoretical calculation at t=0 fs. (b–d) The “ON” state of normalized intensity distribution in the x-y plane from theoretical calculation at t=40 fs, 80 fs and 100 fs, respectively. (e) Transmission of the output of the all-optical switch under different delay time at 1500 nm-1600 nm. (f) Transmission of the output of the all-optical switch under different delay time at 1500 nm.
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Figure 4.
Design optimization process of all-optical XOR logic gate. (a) General configuration of the all-optical XOR logic gate. (b) The initialization and discrete optimization permittivity distribution in the x-y two-dimensional cross-section, where bias=0 and bias=infinity.
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Figure 5.
Characterization of the all-optical XOR logic gate. (a) The “01” input of normalized intensity distribution in the x-y plane from theoretical calculation. (b) The “10” input of normalized intensity distribution in the x-y plane from theoretical calculation. (c) The “11” input of normalized intensity distribution in the x-y plane from theoretical calculation. (d) Scanning electron microscopy (SEM)image of the XOR logic gate. The size of the optimized area was 2 μm×2 μm. (e) Simulation results of the transmission of all-optical switch. (f) Experiment results of the normalized transmission of all-optical XOR logic gate.
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Figure 6.
Characterization of the all-optical integrated circuit. (a) General configuration of the all-optical integrated circuit. (b) The “11” input (“ON” and ”ON” states) of normalized intensity distribution in the x-y plane from theoretical calculation. (c) The “10” input (“ON” and ”OFF” states) of normalized intensity distribution in the x-y plane from theoretical calculation. (d) The “01” input (“OFF” and ”ON” states) of normalized intensity distribution in the x-y plane from theoretical calculation. (e) The “00” input (“OFF” and ”OFF” states) of normalized intensity distribution in the x-y plane from theoretical calculation.
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Figure 7.
Characterization of the all-optical integrated circuit. (a) Scanning electron microscopy (SEM) image of the all-optical integrated circuit. The size of the optimized area was 2.5 μm×7 μm. (b) Simulation results of the transmission of the all-optical integrated circuit. (c) Experiment results of the normalized transmission of the all-optical integrated circuit.
