Research progress of on-chip optical matrix computing chips

Matrix computation, a cornerstone of modern information processing, constitutes the primary computational burden in signal processing and artificial intelligence (AI) algorithms. On-chip photonic matrix computation exploits the inherent high speed and parallelism of optical signals to accelerate operations with low energy consumption and low latency. Moreover, by overcoming the "memory wall" imposed by the separation of memory and processing in the von Neumann architecture, optical computing enables a new paradigm of in-memory computing. As electronic computing approaches its scalability limits and global data volumes continue to expand, photonic matrix computing chips have emerged as a promising solution, demonstrating great potential in artificial intelligence, big data analytics, and high-speed communication systems. This article provides a comprehensive review of the state-of-the-art in photonic matrix computing chips. It outlines the research motivation and development context of this field. Next, the fundamental principles and prevailing on-chip architectures for photonic matrix computation are categorized and analyzed. Following that, the current research landscape is summarized in terms of both chip architectures and practical application scenarios. Finally, this review concludes with a forward-looking discussion on future directions and challenges in photonic matrix computing technology.